`timescale 1ns / 1ps

`include "MIPSCPU_COMMON.vh"

module MemoryAccess(
	mem_enable,
	reg_write_enable,
	reg_write_addr,
	reg_write_hi_enable,
	reg_write_lo_enable,
	reg_written_value,
	mem_out_enable,
	out_reg_write_enable,
	out_reg_write_addr,
	out_reg_write_hi_enable,
	out_reg_write_lo_enable,
	out_reg_written_value
    );
	
	input mem_enable, reg_write_enable;
	input[`REGISTER_ADDRESS_WIDTH - 1 : 0] reg_write_addr;
	input reg_write_hi_enable, reg_write_lo_enable;
	input[`DATA_WIDTH - 1 : 0] reg_written_value;
	output reg mem_out_enable, out_reg_write_enable;
	output reg[`REGISTER_ADDRESS_WIDTH - 1 : 0] out_reg_write_addr;
	output reg out_reg_write_hi_enable, out_reg_write_lo_enable;
	output reg[`DATA_WIDTH - 1 : 0] out_reg_written_value;

	always @(*)
	begin
		mem_out_enable <= mem_enable;
		out_reg_write_enable <= reg_write_enable;
		out_reg_write_addr <= reg_write_addr;
		out_reg_write_hi_enable <= reg_write_hi_enable;
		out_reg_write_lo_enable <= reg_write_lo_enable;
		out_reg_written_value <= reg_written_value;
	end

endmodule
